The present invention relates to a semiconductor memory device using a memory cell constituting a storage electrode in a groove formed in a substrate, and its manufacturing method.
In accordance with high integration of a semiconductor integrated circuit, particularly a semiconductor memory device such as a DRAM (dynamic random access memory), etc., a memory cell area tends to be more and more reduced. In order to meet such a tendency, a semiconductor memory device using a memory cell having a trench capacitor structure has been put to practical use. In this type of the semiconductor memory, an opening portion is formed on a semiconductor substrate, and a storage electrode is structured in the opening portion. As a result, an area of the capacitor area, having a storage electrode and its opposite electrode, can be increased.
In the memory cell having the trench capacitor structure of a substrate plate type having a plate electrode, which serves as the opposite electrode of the storage electrode, and which is formed of the semiconductor substrate, the storage electrode is formed at the interior of the opening portion. As a result, the leakage of stored electrical charges between the adjacent memory cells can be reduced, and the distance between the memory cells can be shortened so as to obtain the structure, which is suitable for high integration of the semiconductor memory device.
FIGS. 1, 2A and 2B are an upper surface view of a conventional memory cell having a trench capacitor structure of a substrate plate type, and its cross-sectional view, respectively.
FIG. 2A is a cross-sectional view taken along a line IIA--IIA as indicated by arrows in FIG. 1, and FIG. 2B is a cross-sectional view taken along a line IIB--IIB as indicated by arrows in FIG. 1.
The memory cell shown in these figures comprises one transistor T1 and one capacitor.
The transistor T1 comprises a gate electrode 5 constituting a word line, and source and drain regions 19a and 19b. The gate electrode 5 is formed on e.g., a p-well, which is formed on a surface region of e.g., an N-type semiconductor substrate 2, through a gate insulating film 3. The source and drain regions 19a and 19b are formed in the p-well 1 to be self-aligned with the gate electrode 5. An insulation film 12 is provided on this gate electrode.
The capacitor is formed in the interior of the opening portion 13 formed in the semiconductor substrate 2. A thick insulating film 14 for an element isolation is formed on an inner wall surface of an upper portion of the opening portion 13. The insulating film 14 is used as a mask, and a capacitor insulating film 16 is formed on the entire inner wall of the opening portion 13.
The storage electrode is buried in the interior of the opening portion 13 through the capacitor insulating film 16 and the insulating film 14. The plate elec trode is formed of the semiconductor substrate 2.
In other words, the capacitor comprises the semiconductor substrate 2, the capacitor insulating film 16, which is formed on the inner wall surface of the opening portion 13, and the storage electrode 8, which is buried in the interior of the opening portion 13.
The storage electrode 8 buried in the opening portion 13 is connected to either one source or the drain region 19a of transistor T1 through a connection electrode 10. As shown in FIGS. 2A and 2B, a bit line 28 is formed to be intersected with a word line 5.
The bit line 28 is connected to either the other source or the drain region 19b of the transistor T1 through a connection 29. In the memory cell structure arranged as in FIG. 1, a capacitor 7 is formed at a lower portion of a passing word line 5. The passing word line 5 passes through a certain memory cell, and does not serve as a gate electrode.
In the conventional memory cell having a trench capacitor structure of a substrate plate type, since the storage electrode 8 is formed in the opening portion 13, the area of the capacitor having the storage electrode 8 and the semiconductor substrate 2 can be increased. Moreover, since the storage electrode 8 is coated with the capacitor insulating film 16, and element isolation insulating films 4 and 14, leakage of stored electrical charges can be controlled. Thus, since the memory cell can be fined and the distance between the adjacent memory cells can be shortened, the semiconductor memory device can be highly integrated.
However, since an area of the opening portion 13 is reduced in accordance with the reduction of the area of the memory cell, the depth of the opening portion 13 must be larger to ensure the capacitance of the capacitor. Generally, it is extremely difficult to equally form the opening portion having a large aspect ratio.
To control the increase of the aspect ratio and increase the capacitance of the capacitor, there is a method in which an insulating film having a high dielectric constant such as Ta.sub.2 O.sub.5 is used as a capacitor insulating film. However, as shown in FIGS. 1, 2A and 2B, in the memory cell structure using the capacitor structure of a trench type, it was difficult to use the high dielectric film as a capacitor insulating film for the following reason:
Specifically, generally, the high dielectric film has a property in which the composition of the film is changed and the dielectric constant is reduced if the heating process of e.g. 750.degree. C. to 800.degree. C. is carried out. For example, in the insulating film containing oxygen such as Ta.sub.2 O.sub.5, there is possibility that the composition will be changed by the heating process (e.g., separation of oxygen).
Also, there is possibility that the insulating film will react with metal constituting the semiconductor substrate 2 or the storage electrode 8 by the heating process of 750.degree. C. to 800.degree. C.
Moreover, in the conventional memory cell having a trench capacitor structure of a substrate plate type as shown in FIG. 1, 2A and 2B, since the capacitor 7 is formed at the lower portion of the passing word line 5, which is formed of the same layer as the gate electrode. Due to this, it is needed that the gate electrode be formed after forming the capacitor 7 in the opening portion 13 to manufacture the above-structured memory cell.
As a result, by the heating process when the gate insulating film 3 is formed under the gate electrode, there is possibility that the film quality of the high dielectric film will be changed or the high dielectlic film will react with the metal constituting the storage electrode 8. However, in the case of using an oxide film (e.g., SiO.sub.2) as a gate insulating film 3, the quality of the gate insulating film 3 intends to be better if the forming temperature is set to be higher. For this reason, the high temperature heating process is required. Thus, there was a contrary requirement.
According to the conventional semiconductor memory device, in the case of using the memory cell having a trench capacitor structure of a substrate plate type in which the capacitor is formed at the lower portion of the passing word line, the gate electrode formed of the same layer as the word line was formed after forming the capacitor.
Moreover, in the case of forming the capacitor insulating film of the high dielectric film, the quality of the high dielectric film was changed by the following heating process. Due to this, it was desirable to carry out the heating process, e.g., processing the gate insulating film after forming the capacitor insulating film.
Therefore, according to the semiconductor memory device having the above-structured memory cell, there was difficulty in using the high dielectric film as a capacitor insulating film.